1. Field of the Invention
The present invention relates to a ring oscillator having a plurality of cascade-connected inverters for generating an output signal of a prescribed cycle by feeding back a signal on an output terminal to an input terminal, and a constant voltage generation circuit incorporating such a ring oscillator.
2. Description of the Background Art
FIG. 15 is a circuit diagram showing a conventional ring oscillator. Referring to FIG. 15, the ring oscillator includes inverters 15, 25, 35, 45, and 55. First stage inverter 15 has its input node connected to the output node of final stage inverter 55, and its output node connected to the input node of second stage inverter 25. The second to fourth stage inverters each have an input node connected to the output node of a preceding stage inverter, and an output node connected to the input node of a succeeding stage inverter.
Although in FIG. 15 the number of stages of the inverters is five, odd-number stages, at least three stages may be provided.
Operation of the ring oscillator in FIG. 15 will be described. When an input signal is input to inverter 15, an output signal OUT which is the inverse of input signal IN is output from final stage inverter 55. Output signal OUT is fed back to the input node of first stage inverter 15, so that output signal OUT becomes a signal inverted in a fixed cycle T as illustrated in FIG. 16.
Now, a description follows in conjunction with FIGS. 17A and 17B on how an oscillation cycle for the ring oscillator is determined. FIG. 17A is a circuit diagram showing in detail first stage inverter 15 and second stage inverter 25 in the ring oscillator in FIG. 15. FIG. 17B is a plan view showing a transistor forming each inverter in FIG. 17A.
Referring to FIGS. 17A and 17B, inverters 15 and 25 each include a PMOS transistor 1p and an NMOS transistor in connected in a complementary manner. PMOS transistor 1p and NMOS transistor in each have an ON resistance value R. Inverters 15 and 25 each have a capacitance C determined by the channel length L and channel width W of each of PMOS transistor 1p and NMOS transistor 1n.
The oscillation cycle T of the ring oscillator is the sum of time delays t of the inverters, and time delay t is represented as follows: EQU t.varies.R.times.C EQU R.varies.L/W, C.varies.W.times.L (1) EQU t.varies.L.sup.2 ( 2)
From expression (2), the time delay t of each inverter is determined by the channel length L of an MOS transistor. Accordingly, in order to prolong the cycle of the output signal, approaches such as (1) to increase the channel length, (2) increase the number of stages of inverters, and (3) to decrease the amount of current supply to the inverters can be considered.
However, increase of R (=L/W) decreases charge/discharge current to/from the gate, but increases C (=W.times.L) as well, and therefore charge/discharge current to/from the gate is conversely increased. Such increase of charge/discharge current increases power consumption by the semiconductor integrated circuit.
Accordingly, in order to reduce power consumption, two approaches, i.e. to increased R and to decrease C are considered.
For example, in order to set 200 ns for the cycle of the ring oscillator shown in FIG. 15, the channel width W/channel length L ratios of PMOS transistor 1p and NMOS transistor 1n are formed to be 1/4, 1/2, respectively. Meanwhile, in order to set 7.6.mu.s for the cycle and 1.7.mu.A for consumption current, as illustrated in FIG. 18, the W/L of PMOS transistor 1p and NMOS transistor in are formed to be 2/50, 2/100, respectively.
FIG. 19 is a circuit diagram showing a ring oscillator incorporated in a PLL circuit disclosed in Japanese Patent Laying-Open No. 3-259619. The ring oscillator serially changes the oscillation cycle by controlling the number of stages of inverters and the amount of current supply to the inverters.
Referring to FIG. 19, the ring oscillator includes a buffer 65, inverters 15-55, and a selector 7. Selector 7 selects the output of third stage inverter 35 or fifth stage inverter 55 in response to a control signal, and feeds back the output to first stage inverter 15. Inverters 15, 25, 35, 45, and 55 each includes PMOS transistors 11p and 12p, and NMOS transistors 11n and 12n connected in series between a power supply node and a ground node. PMOS transistor 11p and NMOS transistor 11n are turned on/off in a complementary manner in response to an input signal. PMOS transistor 12p and NMOS transistor 12n have their ON resistance values changed in response to the output of buffer 65.
In operation, the number of stages of inverters is selected in response to a control signal, and the oscillation cycle is changed. In response to a control voltage, buffer 65 controls the ON resistance values of PMOS transistor 12p and NMOS transistor 12n, and therefore the oscillation cycle can be changed.
In the ring oscillator shown in. FIGS. 15-18, transistors with an increased channel length L are used when an output signal of a long cycle is generated, and therefore resistance value R increases, current flowing from the power supply terminal to the output node and current flowing from the output node to the ground node decrease, thus decreasing current consumption by the ring oscillator.
However, capacitance C increases, and therefore current consumption by the capacitor increases. A ring oscillator with such a large current consumption is not suitable for application to a circuit for generating backup voltage for a memory device, such as to a substrate bias voltage generation circuit.
Transistors 12p and 12n for current limiting shown in FIG. 19 are applied only for a PLL circuit device and used only for serially controlling the oscillation cycle. Accordingly, the oscillation frequency changes around a reference clock signal, and therefore the size of the ring oscillator mostly depends on the gate lengths L of transistors 11p and 11n for switching. Accordingly, in order to provide a ring oscillator with an oscillating cycle of 7.6.mu.s and a current consumption of 1.91.mu.A, for example, the gate lengths L of transistors 11p and 11n for switching must be the same as those shown in FIG. 18. Therefore, the current consumption by input capacitance C cannot be reduced.
FIG. 20 is a circuit diagram showing a ring oscillator for FM-modulating an analog input signal. The circuit is disclosed in Japanese Patent Laying-Open No. 61-147614 (laid open on Jul. 15, 1986).
The ring oscillator shown in FIG. 20 is different from the ring oscillator in FIG. 19 in that PMOSFET 12p and NMOSFET 12n control current in response to an analog input signal.
The circuit shown in FIG. 20 can provide a pulse signal having a frequency corresponding to the level of an analog input signal.
The longest cycle for the pulse signal is about at most ten times as long as the shortest cycle. Accordingly, in order to provide a ring oscillator having a large cycle (7.6.mu.s) and current consumption of 1.91.mu.A, the gate lengths L of transistors 11p and 11n for switching must be the same as those in FIG. 18. Therefore, current consumption due to input capacitance C cannot be reduced.